Dynamic random access memory (DRAM) production typically distinguishes between two main test stages in manufacturing after the processing of the wafer. The first main test stage includes the front end test, also known as the wafer test, which tests the silicon wafer as a whole by means of probe cards contacting the individual chips on the wafer. In this stage of manufacturing, whether defects in the memory area can be repaired by means of fuses is typically decided. The second main test stage is the back end test, also known as the module test, which tests a packaged chip or module after it has been repaired if necessary. In this stage of manufacturing, performing further repairs on a single chip is typically not possible. Therefore, the test performed can be different than the front end test, such that the location and number of fails, if any, are not needed or are needed for statistical purposes only.
Many attempts have been made by manufactures to reduce expensive test time in both the front end test and back end test. One aspect of these efforts is to deviate from the specified interface specification for the memory during test. For example, the interface can be temporarily changed so that not all pads/pins need to be contacted, which saves tester resources. Another example is to enable a test-proprietary timing specification to more efficiently test the chip at non-standardized frequencies.
Front end tests typically need to maintain information about the number and location of fails so that chips that show an acceptable (i.e., repairable) number of fails can be successfully repaired. Back end tests, however, do not need to maintain information about the number and location of fails because the chips typically cannot be repaired at this stage of manufacturing. Back end test systems typically have no means to store the location of a high number of fails or are not able to store locations of fails at all. In typical back end tests, the contents of the memory array are usually read out using the standard user interface specification for the memory, which requires the test systems to be able to read data at a frequency that is relatively high for typically available test equipment and compare the data in real-time with expected data. Using this method, the amount of data being read from a memory device at a given time will be low because of the limitations of the standard user interface (e.g., the number of data output pads).